Analysis & Design of low Power Dynamic Latched Double-Tail Comparator
نویسندگان
چکیده
The need for low power, high speed Analog-To-Digital converters is pushing towards the use of dynamic comparator to maximize speed &power efficiency. In this paper, we designed a Dynamic Latched Double-Tail Comparator which is used in implementation of many ADC’s. An analysis on the delay of the comparator will presented. Simulation results in 0.18um CMOS technology confirm the analysis results. The main idea of this Dynamic Latched Comparator is to reduce the static power consumption by completely cutoff the leakage current to ground. For this purpose, the Power Gating technique is used. The frequency of this comparator is 1GHz at supply voltage of 1.8V.
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